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Combinational circuit analysis and design. State machine analysis and design. Includes synchronous/clock mode circuits and asynchronous sequential circuits. Minimization, race and hazard elimination are covered. Circuits are implemented in discrete logic and in CPLD and FPGA devices. VHDL hardware description language is used to describe circuits. Circuits are implemented in discrete logic and in CPLD/FPGA devices.

Prerequisite(s): ECEN 106.